Design And Reuse

Why Is Manufacturing Data Not Ready to Deliver Manufacturing AI Insights?

Manufacturing plants generates immense amount of data through PLCs, SCADA systems, Historians, MES platforms, Sensors, and ...
Design And Reuse

PFN and Tenstorrent Selected for NEDO Project on "xPU Design and Development Incorporating Photonics Electronics Integration Technology"

Preferred Networks and Tenstorrent to begin R&D of High-Performance and Energy-Efficient AI Processors Incorporating Photonics-Electronics Integration Technology. Preferred Networ ...
Design And Reuse

Multiply Less: Rethinking the Dot Product for Low-Bit Edge AI

Software tests confirmed exact integer equivalence and found floating-point error no worse than the conventional pipeline in the tested cases, and we have sized the design in RTL. Next up: ASIC-level ...
Design And Reuse

Inside the Silicon: Analog Bits N2P2 Test Chip

We are honored to be featured in a recent SemiWiki article discussing our N2P test chip. The future of intelligent computing depends on silicon that delivers more performance within tighter power and ...
Design And Reuse

TSMC plans A14 production for 2028; reported SRAM goal could mean over 19% less bit-cell area

Wccftech reported on October 29, citing DigiTimes, that TSMC’s A14 process was targeted for mass production in the first half of 2028. TSMC’s own plan sets production for 2028. Separately, a reported ...
Design And Reuse

Altera Announces Agilex 2X, a Complete FPGA & SoC Portfolio Built for the Future of Intelligent Systems

Agilex 25 FPGAs deliver a high-performance fabric and embedded compute with optimized I/O, transceivers and peripherals for applications like 4K/8K video processing, drones and low-latency sensors.
Design And Reuse

FuriosaAI Secures $620 Million Series D to Meet Surging Enterprise AI Inference Demand and Accelerate Next-Gen Silicon

FuriosaAI, an AI semiconductor company building sustainable, high-performance inference compute for data centers, today announced the completion of its $620 million (KRW 820 billion) Series D round, ...
Design And Reuse

VeriSilicon Introduces GLTiny™ 3D GPU Programming Model for Ultra-Low-Power, Memory-Efficient Wearable Devices

VeriSilicon (688521.SH) today announced GLTiny, an innovative 3D Graphics Processing Unit (GPU) programming model designed for wearable devices with stringent power and memory constraints. Featuring a ...
Design And Reuse

Nordic Semiconductor proves Bluetooth High Data Throughput feature in silicon

Nordic Semiconductor, a global leader in low-power wireless connectivity solutions, today became the first to prove the upcoming Bluetooth® High Data Throughput (HDT) feature in silicon. Nordic is ...
Design And Reuse

Q&A: Bringing Co-Packaged Optics to AI Infrastructure

Traditionally, fiber brings data up to the front panel of a rack and then copper takes over. Optical signals are converted to electrical signals, which then travel to compute, memory, or other ...
Design And Reuse

DCD-SEMI at electronica 2026 in Munich

DCD-SEMI will participate in electronica 2026, the world’s leading trade fair and conference for electronics, from 10–13 November 2026 at Messe München, Munich, Germany. Founded in 1999, DCD-SEMI has ...
Design And Reuse

Nuclei Releases the Nuclei Studio VS Code IDE Preview: A Lighter, More Modern RISC-V Development Experience

Shenzhen, China — Nuclei, a leading provider of high-performance semiconductor IP processing solutions, officially released ...